The present invention relates to execution of host-initiated I/O operations in a fibre channel node, and, in particular, to a method and system for carrying out completion of I/O operations in a fibre channel node with fewer data transfers between interface-controller and host-computer components of the fibre channel node and with allocation of less host-memory resources, than in previous and current fibre-channel-node implementations.
The fibre channel (xe2x80x9cFCxe2x80x9d) is an architecture and protocol for a data communications network for interconnecting computers and peripheral devices. The FC supports, a variety of upper-level protocols, including the small computer systems interface (xe2x80x9cSCSIxe2x80x9d) protocol. A computer or peripheral device is linked to the network through an FC port and an FC link comprising copper wires or optical fibres, the computer or peripheral device, FC port, and FC link together referred to as an xe2x80x9cFC node.xe2x80x9d An FC port includes a transceiver and an interface controller, and the computer or peripheral device in which the FC port is contained is called a xe2x80x9chost.xe2x80x9d Hosts generally contain one or more processors, referred to as the xe2x80x9chost processorxe2x80x9d in the current application. The FC port exchanges data with the host via a local data bus, such as a peripheral computer interface (xe2x80x9cPCIxe2x80x9d) bus. The interface controller conducts lower-level protocol exchanges between the fibre channel and the computer or peripheral device in which the FC port resides.
An interface controller within an FC port serves essentially as a transducer between the serial receiver and transmitter components of the FC port and the host processor of the FC node in which the FC port is contained. The interface controller is concerned with, on the input side, assembling serially-encoded data received from the receiver component into ordered sets of bytes, assembling a majority of the ordered sets of bytes into basic units of data exchange, called xe2x80x9cFC frames,xe2x80x9d and passing the FC frames, along with status information, to the host processor within the context of larger collections of FC frames, called FC sequences and FC exchanges. On the output side, the interface controller accepts host memory buffer references and control information from the host processor, transforms them into FC frames, within higher-level contexts of FC sequences and FC exchanges, and provides the FC frames to the transmitter component of the FC port for serial transmission to the FC. The interface controller also exchanges lower-level control messages with remote nodes via the fibre channel that are used for configuring the fibre channel, maintaining state within fibre channel nodes, establishing temporary paths between nodes, arbitrating control of fibre channel loops, acknowledging receipt of data frames, and extending data transfer credits to remote nodes, among other things.
The interface controller communicates with the host processor through a set of host memory-based data structures and through a number of control registers accessible to both the interface controller and the host processor via a local bus, such as a PCI bus. At any given instant, the interface controller may be handling outgoing FC frames associated with different FC sequences, and may be also handling inbound FC frames from the FC associated with a number of FC sequences. The interface controller uses internal caches to cache information from the host memory-based data structures with which the interface controller communicates with the host processor.
The interface controller plays an analogous function within an FC port as that played by a computer processor in a multi-tasking operating system environment. The interface controller handles many different events concurrently with extremely dynamic patterns of state changes and information flow. The state of an interface controller is maintained in a number of different dynamic data structures and queues, generally stored within host memory, and accessible to both the interface controller and the host. The state of each currently active FC exchange and FC sequence is maintained in these data structures, as well as descriptors that reference incoming and outgoing frames, completion messages for write and read operations, and other such information.
I/O operations may be conducted within the context of a SCSI I/O operation embedded within the fibre channel protocol. An I/O operation is initiated by an initiator node in order to read data from, or write data to, a target node. At the conclusion of a write or read operation (xe2x80x9cI/O operationxe2x80x9d), the initiator node generally receives a FC response frame from the target node, whether or not the I/O operation successfully completes. This FC response frame is received by the interface controller from the fibre channel, the data contents of the FC response frame are transferred to a buffer in host memory, and a completion notice is placed into a separate completion queue in host memeory by the interface controller. Thus, data is sent from the interface controller to two different host memory locations upon reception by the initiating node of a response FC frame.
In FC controllers, as in operating systems and other real-time device controllers, memory resources are scarce, and unnecessary data transfers can decrease data transfer bandwidth through buses and slow overall data throughput. FC controller designers and manufacturers have therefore recognized a need to decrease the memory resources allocated for I/O operations and decrease the number of data transfers between an FC controller and host memory during I/O operations between FC nodes.
The present invention provides a method and system for efficient completion of I/O operations within an FC node. When the FC port of the FC node receives an FC response frame from a target node as the last FC frame of an exchange of FC frames between the FC node and the target node representing an I/O operation, the FC port analyzes data in the FC response frame to determine whether or not the I/O operation completed successfully. If the I/O operation completed successfully, then the FC port queues a completion message with an indication of successful completion to a queue maintained in host memory, avoiding transmission of the FC response frame to host memory through a bus interconnecting the FC port with host memory. If, on the other hand, analysis of the FC response frame by the FC port results in a determination that the I/O operation did not successfully complete, then the FC port queues a portion of the response frame to a single frame queue within host memory and queues a completion message to the message queue in host memory with an indication that the I/O operation did not successfully complete.
By the method and system of the present invention, the host processor of the FC node does not need to allocate memory buffers to contain the data portion of the FC response frame returned at the end of an I/O operation from the target node. Instead, the host processor can determine whether an I/O operation successfully completed by examining a bit field within a completion message queued to a message queue within host memory. If an I/O operation does not successfully complete, as indicated by the bit flag within the completion message, the host processor can use identification information included in, or referenced by, the completion message to locate the FC response frame returned by the target node upon unsuccessful completion of the I/O operation within a single frame queue in host memory. Because I/O operations generally successfully complete, queuing of FC response frames to the single frame queue of the FC port is a relatively infrequent event. Thus, by the method and system of the present invention, the host processor allocates less memory for each I/O operation than in prior art methods and systems, and the transmission overhead associated with transmitting FC response frames from the FC port to host memory is largely eliminated. This, in turn, result in expenditure of fewer host processor cycles per I/O operation, a decrease in host memory bus utilization, higher data throughput to and from the FC node, and a decrease in I/O latency with respect to prior art methods and systems.